1. Field of the Invention
The present invention relates to apparatus and methods for a bi-CMOS differential amplifier, and more particularly to a high speed bi-CMOS differential amplifier with controlled output voltage swing for use with low level complementary logic signals.
2. Art Background
Differential amplifiers are commonly used in bi-level signal processing, wherein the magnitude of one signal is compared to the magnitude of another, and the output determined by the difference between the two signals. For MOSFET constructions, including bi-CMOS constructions, a common method of optimizing the differential amplifier for a particular application is to drive a current through a resistive load. Referring to FIG. 1a, a differential amplifier 115 is shown, formed by a pair of bipolar transistors 110 and 111, with current supplied by a current source 112. The output of differential amplifier 115 is equal to the voltage difference across a pair of resistive loads 100 and 101 connected to each bipolar transistor 110 and 111 forming differential amplifier 115. Resistive loads 100 and 101 are chosen such that the voltage drop across each produces a voltage difference which is appropriate for the particular parameters of the circuit elements which follow differential amplifier 115.
Although the resistive load matching circuit shown in FIG. 1a works well for many applications, the design falters when applied to high speed logic processing. There are two predominant performance problems associated with the above-mentioned resistive load configuration. First, if the voltage swing across either resistive load 100 or 101 is too large, then either transistor 110 or 111 connected to the load can be driven into saturation, i.e., the collector-base junction becomes forward biased. Once the transistor has saturated, turning the transistor off requires more time, and therefore will retard the performance of the differential amplifier.
Secondly, although the excessive voltage swing can be reduced through the use of voltage clamps, the solution itself induces another problem. Referring now to FIG. 1b, a differential amplifier 165 is formed by a pair of bipolar transistors 160 and 161, with current supplied by a current source 162. As shown in FIG. 1b, the swing voltage of differential amplifier 165 is reduced through the use of a pair of bipolar clamps 150 and 151 limiting the output of loads 140 and 141 driven by transistors 160 and 161 respectively. However, the presence of clamps 150 and 151 in and of themselves increases the capacitance on the output nodes. If the capacitance is too high, the time response to time-varying signals is increased which again results in a slowing of the response for that output node, and therefore retards the overall performance of differential amplifier 165. As suggested above, both the saturation and capacitance conditions cause significant problems in a circuit where speed is crucial.
Moreover, depending on the particular application, the physical size of the resistive load can result in a slowing of circuit performance. Typically, a resistor in a MOSFET device is formed as a base-diffusion transistor operating within the linear response region of its associated I-V characteristic. As such a base-diffusion resistor is physically layed out on the silicon substrate, the intrinsic capacitance of the resistive device increases with increasing physical size of the device. The increased capacitance of the device results in slowing the response of the node. At some point, the slowing can render the amplifier useless for high or very high speed applications.
Another prior art solution to the differential amplifier optimization problem is to use an active feedback mechanism to relate differential amplifier output voltage to the reference voltage source. Although this solution can provide more precise output voltage control, active feedback can be inappropriate when applied to high speed circuits. In very high speed logic circuits, the mere measurement of the output node can raise the node capacitance to appreciably slow the performance of the node, and thereby slow the performance of the entire differential amplifier.